1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly, to integrated circuit devices having high data bandwidth..
2. Description of the Related Art
Generally, semiconductor memory devices have a high bandwidth input/output (I/O) structure, and may include 32 data output pins, or DQ pins. In such a high bandwidth memory device, the 32 DQ pins may operate at the same time when data is output, resulting in a great amount of noise, known as simultaneous switching noise (SSN). Due to SSN, waveforms of data output signals may be distorted, which may deteriorate signal integrity of the memory device. As such, it may be difficult for the memory device to satisfy the input/output performance required in a high-frequency system. For this reason, conventional techniques to reduce SSN have included the use of data inversion circuits.
Data inversion methods may aim to reduce the amount of SSN generated in memory devices by limiting the number of parallel data signals that switch value during consecutive data output cycles. A memory device using the data inversion method may either invert and output current data or output the current data without inversion based on how many bits of data (generally, 8 bits) to be currently output are switched or “toggled” as compared to corresponding bits of previously output data. More particularly, if the number of toggled bits is greater than or equal to one-half of the number of bits to be currently output, the memory device may invert and output the data, and additionally may output a flag signal of 1-bit indicating that the data was inverted. On the other hand, if the number of toggled bits is less than one-half of the number of bits to be currently output, the memory device may output the data without inversion, and may additionally output a flag signal of 1-bit indicating that the data was not inverted. As such, the number of bits of the output data to be toggled can be reduced to less than half of the total number of bits to be output, and accordingly, switching noise in the memory device can be reduced. As a result, the signal intensity of output signals may be improved, such that input/output performance of the memory device may also be improved.
FIG. 1 illustrates a conventional data inversion circuit. FIG. 1 shows a data inversion circuit that performs inversion/non-inversion on 8-bit data to be output to 8 data output pads (DQ pads).
Referring to FIG. 1, the data inversion circuit 10 includes logic circuits 11 and 12 and a comparator 13. Each of the logic circuits 11 and 12 includes 8 XOR gates. The logic circuit 11 determines whether or not bits of data FDO1 through FDO8 to be currently output (which are read from a memory cell), are to be toggled based on corresponding bits of data DO1 through DO8 which were previously output from the data inversion circuit 10. The comparator 13 outputs a flag signal FLG with a predetermined level according to the determined result of the logic circuit 11. The logic circuit 12 inverts and outputs the data FDO1 through FDO8 to be currently output, or alternatively, outputs the data FDO1 through FDO8 without inversion, in response to the flag signal FLG.
As described above, a conventional data inversion circuit may determine whether or not each bit of the previous data (which may have been output in an inverted state or in a non-inverted state) is toggled compared to a corresponding bit of data to be currently output, in order to decide whether the data to be currently output should be inverted or should not be inverted. The previously output data and the data to be currently output may be continuous or non-continuous. In other words, an interval in which no data is read (i.e., an interval where no read instructions are received) may exist between a time when the previous data has been read and a time when the data to be currently output is read. For example, a time interval (i.e., a reading interval) between receipt of a first read command for reading first data and receipt of a second read command for reading second data may exceed a predetermined time interval. In such a case, the data output circuit of the memory device may achieve a stable state during this time interval. Once the data output circuit reaches a stable state, SSN may not be generated in the data output voltage.
However, a conventional data inversion circuit may be inefficient in that an inversion operation may be performed on the data to be currently output regardless of the presence of a reading interval between the previous data and the data to be currently output. In other words, the current output may be inverted to inhibit SSN even though SSN may not be present because of an extended reading interval where no switching is performed. Also, such an inversion operation may reduce the operating speed of the semiconductor device.
Also, a conventional data inversion circuit may compare data to be currently output with previously output data in order to decide whether or not the data to be currently output should be inverted. The previously output data may have been subjected to inversion/non-inversion, while the data to be currently output is data before being subjected to inversion/non-inversion. Accordingly, a timing margin may exist between the previous data and the data to be currently output. Such a timing margin may further reduce the operating speed of the data inversion circuit, and may limit the operational frequency of the semiconductor device.